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The present invention relates generally to the forming of features in the surface of a semiconductor substrate and, more specifically, to the formation of a raised region in an integrated circuit device.
Description of the Related Art
In the manufacture of integrated circuit semiconductor devices, dielectric or non-conductive layers are formed over a substrate. Conductive regions are then formed in the layers and various interconnect structures are formed between the layers and the conductive regions. Examples of such interconnect structures include, but are not limited to, plugs formed in a dielectric layer to connect conductive regions in a previous layer to a conductive region in a subsequent layer, and inter-level dielectric (ILD) layers formed between multiple layers of conductive regions.
Within the semiconductor substrate, conductive material is deposited to form the conductive regions and the interconnect structures. These steps are normally performed by a deposition step in which a conductive material is deposited and a planarization step in which the conductive material is removed from the substrate except where it is later used as part of an interconnect structure. To planarize the conductive material, it is often desirable to form raised regions in the surface of the substrate, for example, to create an interconnect structure. A raised region may be formed by selectively etching through a dielectric or other material that is formed over a substrate.
Raised regions are typically formed using etching techniques that are selective to one conductive material over another conductive material. For example, a raised region may be formed by etching one or more materials within the dielectric. In the

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